New Low-Latency Cache Protocol for NAND Flash Memory
Published on November 12, 2023
Our R&D team has presented a significant advance in cache management for high-density embedded systems, reducing write latency by 22%.
Current micro-storage architecture faces the bottleneck between the processor and non-volatile memory. Traditional cache protocols introduce overhead that is critical in real-time applications.
The new proposal, called FlashSync, implements a deferred write algorithm with an intelligent pre-buffer, optimizing NAND cell cycles and extending its lifespan. Tests in controlled environments with intensive workloads show a sustained improvement in throughput.
Benchmark Test Results
Validation was performed on a custom development board, comparing FlashSync with standard industry methods. The collected data confirms the latency reduction and better wear-leveling management.
The next step is the integration of the protocol into our upcoming controller chip, whose launch is scheduled for the second quarter of next year.